1. Field of the Invention
The present invention relates to a position aligning apparatus, a position aligning method, and a semiconductor device manufacturing method. Especially, the present invention relates to a position aligning apparatus, a position aligning method, and a semiconductor device manufacturing method, which are used for a position alignment of a pattern in a pattern exposure process.
2. Description of Related Art
An exposure process in which a mask pattern is aligned on a semiconductor wafer and then the wafer is exposed is executed in a photolithography process of a semiconductor device manufacturing method. The exposure process requires an operation of accurately position-aligning a mask pattern to be used next on a pattern provided on the semiconductor wafer. The position alignment is carried out by using a position aligning mark formed on the semiconductor wafer.
FIG. 1 is a schematic diagram showing an example of a semiconductor wafer in manufacturing a semiconductor device. A semiconductor wafer 50 has a region 51 for semiconductor chips. The region 51 includes a plurality of chip regions 53 and a plurality of scribe regions 54. The plurality of chip regions 53 are arranged on an approximate matrix, and serve as semiconductor chips (semiconductor devices), respectively. The plurality of scribe regions 54 are provided between every adjacent two of the plurality of chip regions 53, and the wafer is scribed at the positions when the semiconductor chip has been manufactured.
FIG. 2 is a schematic diagram showing an example of a region 52 (a region surrounded by a dashed line) in FIG. 1. In the region 52, the scribe regions 54 around the chip region 53 have position aligning marks 61 and position aligning check marks 62 and 63, as marks for the above-mentioned position alignment. The position aligning mark 61 is used to superpose a mask pattern on a pattern provided on the semiconductor wafer by an exposing apparatus. The position aligning check mark 62 is provided almost directly above the position aligning check mark 63 of the pattern on a lower side on the semiconductor wafer. The position aligning check mark 62 is used for checking completeness of the pattern, the completeness being degree of misalignment of a pattern formed through this position alignment from an appropriate position based on a position relation with the position aligning check mark 63 of the pattern on the lower side. A value showing the degree of misalignment of the pattern formed at this position alignment from an appropriate position is, for example, called a completeness value.
FIG. 3 is a cross sectional view showing an example of the scribe region 54 in FIG. 2. In the semiconductor device, a plurality of layers 70 are generally stacked. The respective layers are provided with the position aligning marks 61 and the position aligning check marks 62 and 63. In this example, layers 70-1 to 70-6 are stacked. In addition, the layer 70-1 has a position aligning mark 61-1 and position aligning check marks 62-1 and 63-1. Similarly, the layers 70-2 to 70-6 have the position aligning marks 61-2 to 61-6 and the position aligning check marks 62-2 to 62-6 and 63-2 to 63-6, respectively. In the semiconductor device in this example, the position aligning mark 61 is formed in all of the layers 70. Specifically, the each layer 70 is formed in a “direct position aligning” process of superposing a mask pattern on a pattern provided on a semiconductor wafer by using the position aligning mark 61 on a layer lower by one layer. For example, in case of forming the layer 70-3, the mask pattern is superposed on the pattern provided on the semiconductor wafer by using the position aligning check mark 61-2 on the layer 70-2 lower by one layer.
FIG. 4 is a cross sectional view showing another example of the scribe region 54 in FIG. 2. In comparison with FIG. 3, the position aligning mark 61 is not necessarily formed in all the layers 70 in this example. For example, while the position aligning mark 61 is formed in the layers 70-1, 70-3, and 70-5, the mark is not formed in other layers 70-2, 70-4, and 70-6. This means that the layers 70-2, 70-4, and 70-6 are formed in the above-mentioned direct position aligning process. However, the layers 70-3 and 70-5 are formed in an “indirect position aligning” process in which the exposure apparatus superposes a mask pattern on a pattern provided on the semiconductor wafer by using the position aligning mark 61 other than the position aligning mark 61 on a layer lower by one layer. For example, in case of forming the layer 70-3, since there is not the position aligning mark 61 on the layer 70-2 lower by one layer, the mask pattern is superposed on the pattern provided on the semiconductor wafer by using the position aligning mark 61-1 on the layer 70-1 lower by two layers.
In the above-mentioned position aligning process of superposing the mask pattern on the pattern provided on the semiconductor wafer, it is known that several types of position misalignment occur. FIGS. 5A to 5D and 6A to 6C are schematic diagrams showing examples of the position misalignment occurring in the position alignment. The drawings show that chip regions 53a (dashed lines) are in a lower layer and that chip regions 53b (solid lines) are in an upper layer. As the types of position misalignment, two types exist: one is a position misalignment shown in FIGS. 5A to 5D, regarding the whole of a plurality of chip regions 53, and the other is the position misalignment shown in FIGS. 6A to 6C, regarding the respective regions 53. Specifically, as the position misalignment regarding the whole of the plurality of chip regions 53, three types exist; the first is a shift misalignment in an X and a Y directions (ShiftX and ShiftY) shown in FIG. 5A, the second is a scale misalignment in the X and the Y directions (WaferScaleX and WaferScaleY) shown in FIG. 5B, and the third is a rotation misalignment in the X and the Y directions (WaferRotation X and WaferRotation Y) shown in FIGS. 5C and 5D. As the position misalignment regarding the respective regions 53, two types exist; one is a scale misalignment in the X and the Y directions (ShotScaleX and ShotScaleY) shown in FIG. 6A, and the other is a rotation misalignment in the X and the Y directions (ShotRotation X and ShotRotation Y) shown in FIGS. 6B and 6C.
There are proposed various types of methods of correcting the position misalignment and suppressing their influences, when the exposure apparatus superposes a mask pattern on a pattern provided on the semiconductor wafer. As such a correcting method, Japanese Patent Application Publication (JP-P2006-73986A corresponding U.S. Pat. No. 7,220,521 B2) discloses a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device intends to improve accuracy of estimating a correction parameter set to the exposure apparatus for the position misalignment of a chip balance center other than the shift misalignment (ShiftX and ShifY). The method of manufacturing the semiconductor device includes an exposure process of: forming a lower-side pattern by a first exposure; and forming an upper-side pattern by a second exposure. The method of manufacturing the semiconductor device includes: a first exposure process of, in an immediately-preceding lot for which the exposure process is carried out immediately before a current lot, aligning a position of the upper-side pattern with respect to the lower-side pattern on a processed substrate on which the lower-side pattern is formed by the first exposure and exposing the processed substrate by the second exposure; and a second exposure process of, in the current lot, aligning a position of the upper-side pattern with respect to the lower-side pattern on the processed substrate on which the lower-side pattern is formed by the first exposure and exposing the processed substrate by the second exposure. Moreover, the method includes: a process of obtaining a first correction value indicating a difference between a first setting value of position misalignment correction parameter (P0set (ChipMagX, Lj) and a second setting value of position misalignment correction parameter (P0set (ChipMagX, Lj−1) each of which was used for aligning the position of the lower-side pattern in exposing the lower-side pattern on a current lot (Lj) and an immediately-preceding lot (Lj−1); a process of obtaining an optimum correction value (P1result (ChipMagX, Lj−1)) required to accurately align the position of the upper-side pattern as a second correction value with respect to a third setting value of position misalignment correction parameter (P1set (ChipMagX, Lj−1) used in exposing the upper-side pattern on the immediately-preceding lot (Lj−1), a process of obtaining an estimation value of optimum correction parameter (Estimate (ChipMagX, Lj)) used in exposing the upper-side pattern on the current lot (Lj) on the basis of the first correction value and the second correction value, and a process of carrying out exposure by using the estimation value of optimum correction parameter when the upper-side pattern is exposed on the current lot in the second exposure process.
In addition, Japanese Patent Application Publication (JP-P2007-27429A corresponding US Patent Application Publication (US 2007/020537 A1)) discloses an exposure apparatus correcting system, an exposure apparatus correcting method, and a method of manufacturing a semiconductor device. The exposure apparatus correcting system includes a misalignment calculating section, an approximating section, a rounding section, a back-calculating section, a residual calculating section, an estimation amount memory section, and a control section. The misalignment calculating section calculates position misalignment between a transcribed first test pattern and a second test pattern transcribed after its position has been aligned to the first test pattern. The approximating section approximates a relation between the position misalignment and a coordinate system including the second test pattern by using a plurality of parameters. The rounding section rounds a plurality of parameters within an effective range restricted by the exposure apparatus that transcribed the second test pattern. The back-calculating section calculates misalignment between the first test pattern and the second test pattern by using the rounded value as an estimated amount. The residual calculating section subtracts the calculated misalignment from the position misalignment. The estimation amount memory section stores an estimated amount. The control section corrects the exposure apparatus on the basis of summation of the estimated amount stored in the estimation amount memory section to reduce the position misalignment.
In recent years, as a progress of a finer process in a semiconductor integrated circuit, a technique is demanded which can carry out position alignment with high accuracy. To carry out the position alignment with high accuracy, it is required to improve an accuracy of correction of position misalignment. Meanwhile, as the semiconductor integrated circuit is highly integrated, the number of TEGs (Test Element Group) to be mounted increases and multilayer wiring has been used. Since the number of marks for position alignment is reduced due to an increase of the number of the TEGs, the above-mentioned indirect position aligning process has been introduced. Additionally, when the multilayer wiring has been used, stress applied to a semiconductor wafer varies in a manufacturing process. Variations of completeness between lots cannot be ignored in order to carry out the position alignment with extremely-high accuracy in such a situation. However, a conventional method of correcting the position misalignment (for example, Japanese Application Patent Publication (JP-P2006-73986A)) considers variations between processes but does not consider the variations of completeness between such lots. For this reason, it is believed that the position alignment with extremely-high accuracy is difficult. A technique is desired which can carry out the position alignment with higher accuracy in both of the direct position aligning process and the indirect position aligning process.
[Citation List]
                [Patent Literature]                    [PTL 1] JP-P2006-073986A            [PTL 2] JP-P2007-027429A                        